1. Field of the Invention
The present invention relates to a computer system, and more particularly to a control system for a peripheral circuit suitable for reducing the machine cycle or bus cycle of the operation.
2. Related Background Art
In a prior art computer system, a peripheral circuit of a CPU is controlled, by sending a control signal necessary to the peripheral system by way of a peripheral control circuit or bus controller, which operates in synchronism with the CPU in response to a basic clock supplied to the CPU, for carrying out necessary operations (for example, generation of an access signal to a memory or I/O) by the peripheral system by making use of the control signal to attain exchange of data between the CPU and the memory or the I/O. Several bus controllers of different functions may be used, but usually one bus controller controls many units in the system.
As an example of such systems, a system is shown in FIGS. 31 and 32 of Intel Microprocessor and Peripheral Handbook, 3-34 and 3-35, Vol. 1-Microprocessor, Document No. ISBNI-55512-062-8. FIG. 31 thereof shows a basic system comprising one bus controller and one CPU and having a local bus. A clock (CLK) which provides a reference for system operation is generated by a clock generator and it is directly supplied to both the bus controller and the CPU. FIG. 32 thereof shows a system configuration for a special case where a multi-bus, which is a system bus, is to be controlled. It has basically the same configuration as that of FIG. 31 except for the addition of a bus arbiter which generates a signal required by the multi-bus. The CLK signal from the clock generator is also directly supplied to the bus arbiter. The bus arbiter generates a signal to control the bus controller (for example, AEN signal) and it is serially supplied to the bus controller. In any basic system, a sub-control system in the system and sub-systems on the bus are controlled by using the control signal of the control system.
As an alternative system configuration, FIGS. 31 and 32 of the above reference are combined to include both local bus and system bus a and distributed bus control systems are provided to control the local bus and the system bus, respectively. In this case, the control of the respective buses is carried out through the respective bus control systems.
In the prior art system, a synchronization signal to the peripheral control circuit and the bus controller is usually the same as (or equivalent to) the clock supplied to the CPU and it is not of advanced phase (signal transition occurs at an earlier time). Accordingly, the control signal outputs from the peripheral control circuit and the bus controller are delayed by the time required to pass through the peripheral circuit and the bus controller, relative to the reference clock supplied to the CPU. Therefore, in the peripheral system which uses such control signal, a further delay time (gate delay or delay due to the machine cycle) is included in the course of generating the access signal to the memory. As a result, a high speed machine cycle or bus cycle cannot be attained. Further, in a system in which one peripheral control circuit or bus controller controls the peripheral system, a signal load is so heavy that the signals are delayed, or signal lines are so long that the system is not electrically stable.